library verilog;
use verilog.vl_types.all;
entity modelodereferencia is
    port(
        clock_27_ref    : in     vl_logic;
        clock_50_ref    : in     vl_logic;
        borda_ref       : in     vl_logic;
        binarizacao_ref : in     vl_logic;
        mostra_gray_ref : in     vl_logic;
        reset_ref       : in     vl_logic;
        thrashhold_ref  : in     vl_logic_vector(9 downto 0);
        pixel_ref       : in     vl_logic_vector(9 downto 0);
        pixel_valido_ref: in     vl_logic;
        pixel_convoluido_ref: out    vl_logic_vector(9 downto 0);
        ok              : out    vl_logic
    );
end modelodereferencia;
